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  • Undergraduate Poster Abstracts
  • THU-737 FPGA PROTOTYPING AND SOFTWARE CONSTRUCTION FOR ASIC AND USB INTERFACES FOR A STEREO VISION HARDWARE ACCELERATOR

    • Sungil Kim ;
    • Ziyun Li ;
    • Hun-Seok Kim ;
    • David Blaauw ;

    THU-737

    FPGA PROTOTYPING AND SOFTWARE CONSTRUCTION FOR ASIC AND USB INTERFACES FOR A STEREO VISION HARDWARE ACCELERATOR

    Sungil Kim1, Ziyun Li, Hun-Seok Kim, David Blaauw.

    University of Michigan, Ann Arbor, MI.

    ASIC (application-specific integrated circuits) development cost is increasing due to emerging design and computational complexity while time to market is decreasing due to fast-growing technology. To reduce potential failures and cost, ASIC designs that use FPGA (field-programmable gate array) prototyping to verify functionality of the circuit are both effective and reliable, especially for real-time systems like stereo cameras. We develop a faster stereo vision hardware accelerator that consumes less power than a GPU-based stereo camera by addressing the data communication between the ASIC chip, FX3, and host PC. Streaming from the chip and into the chip also needs verification. This study determines the extent to which functionality of ASICs and the interface between the chip and USB peripheral controller (FX3) can be verified. Coupled with software verification, FPGA adjusts the logic behavior of the chip to run at near real time with data transfer rate of 2 gigabits per second. As the interface between ASIC and FX3 involves 12 signals: clock, flags, read/write strobe, address, and 32-bit data, debugging of the behavior requires designers to observe real-time signals and transitions. Using Xilinx ChipScope Pro, we verify the handshaking and timing. From the host side, we prototype with compatible software libraries for USB interfaces. After processing left and right images, the developed software verifies the bidirectional data transfer. These results suggest FPGA prototyping is particularly effective for handling real-time signals. The verifying step via FPGA prototyping can significantly reduce chip failure and manufacturing cost and increase design pace.